TPS2491DGSG4【PDF 10/25 页】IC POS HV HOT-SWAP CTRLR 10-MSOP

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Sheet目录47

6页 7页 8页 9页 [10页]11页 12页 13页 14页

LIM

J(MAX)

* T

S(MAX)

qJC(MAX)

PROG

LIM

10 I

LIM

TPS2490

TPS2491

SLVS503D NOVEMBER 2003REVISED JULY 2012

www.ti.com

(2)

where P

LIM

is the desired power limit of M1 and I

LIM

is the current limit setpoint (see SENSE). P

LIM

is determined

by the desired thermal stress on M1:

(3)

where T

J(MAX)

is the maximum desired transient junction temperature of M1 and T

S(MAX)

is the maximum case

temperature prior to a start or restart.

PROG

is used in conjunction with V

to compute the (scaled) current, I

D_ALLOWED

, by the constant power engine.

D_ALLOWED

is compared by the gate amplifier to the actual I

, and used to generate a gate drive. If I

D_ALLOWED

, the amplifier turns the gate of M1 fully on because there is no overload condition; otherwise GATE is

regulated to maintain the I

= I

D_ALLOWED

relationship.

A capacitor may be tied from PROG to ground to alter the natural constant power inrush current shape. If

properly designed, the effect is to cause the leading step of current in Figure 13 to look like a ramp.

PROG is internally pulled to ground whenever EN, POR, or UVLO are not satisfied or the TPS2490 is latched off.

This feature serves to discharge any capacitance connected to the pin. Do not apply voltages greater than 4 V to

PROG. If the constant power limit is not used, PROG should be tied to VREF through a 47-k& resistor.

TIMER: An integrating capacitor, C

, connected to the TIMER pin provides a timing function that controls the

fault-time for both versions and the restart interval for the TPS2491. The timer charges at 25 礎 whenever the

TPS2490/91 is in power limit or current limit and discharges at 2.5 礎 otherwise. The charge-to-discharge current

ratio is constant with temperature even though there is a positive temperature coefficient to both. If TIMER

reaches 4 V, the TPS2490 pulls GATE to ground, latch off, and discharge C

. The TPS2491 pulls GATE to

ground and attempt a restart (re-enable GATE) after a timing sequence consisting of discharging C

down to 1 V

followed by 15 more charge and discharge cycles. The TPS2490 can be reset by either cycling the EN pin or the

UVLO (e.g. power cycling). TIMER discharges when EN is low or UVLO or POR are active. The TIMER pin

should be tied to ground if this feature is not used.

PG: This open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PG

goes open-drain (high voltage with a pull-up) after V

of M1 has fallen to about 1.25 V and a 9 ms deglitch time

period has elapsed. PG is false (low or low resistance to ground) whenever V

of M1 has not been less than

1.25 V, V

of M1 is above 2.7 V, or UVLO is active. Both V

rising and falling are deglitched while entering

UVLO sets PG low immediately. PG can also be viewed as having an input and output voltage monitor function.

The 9-ms deglitch circuit operates to filter short events that could cause PG to go inactive (low) such as a

momentary overload or input voltage step. V

voltage can be greater than V

VCC

because its ESD protection is

only with respect to ground.

GND: This pin is connected to system ground.

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